----------------------------------------------------------------------- -- 4 * 4 multiplexer -----入力振り分け用 4 * 4ch スイッチャー ----------------------------------------------------------------------- library IEEE; --ライブラリ宣言 use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux4 is　　　　　　　　　　　　　 　　　　　　　　--ポート宣言 Port ( d16: in std_logic_vector (15 downto 0); swBus: in std_logic_vector (3 downto 0); out0: out std_logic; out1: out std_logic; out2: out std_logic; out3: out std_logic); end mux4; architecture RTL of mux4 is --アーキテクチャ begin out3 <= ((d16(15) or d16(14) or d16(13) or d16(12)) or (swBus(0) and (d16(3) or d16(2) or d16(1) or d16(0))) or (swBus(1) and (d16(7) or d16(6) or d16(5) or d16(4))) or (swBus(2) and (d16(11) or d16(10) or d16(9) or d16(8)))); out2 <= ((d16(11) or d16(10) or d16(9) or d16(8)) or (swBus(0) and (d16(3) or d16(2) or d16(1) or d16(0))) or (swBus(1) and (d16(7) or d16(6) or d16(5) or d16(4))) or (swBus(3) and (d16(15) or d16(14) or d16(13) or d16(12)))); out1 <= ((d16(7) or d16(6) or d16(5) or d16(4)) or (swBus(0) and (d16(3) or d16(2) or d16(1) or d16(0))) or (swBus(2) and (d16(11) or d16(10) or d16(9) or d16(8))) or (swBus(3) and (d16(15) or d16(14) or d16(13) or d16(12)))); out0 <= ((d16(3) or d16(2) or d16(1) or d16(0)) or (swBus(1) and (d16(7) or d16(6) or d16(5) or d16(4))) or (swBus(2) and (d16(11) or d16(10) or d16(9) or d16(8))) or (swBus(3) and (d16(15) or d16(14) or d16(13) or d16(12)))); end RTL;　　　　　--1group 4ch スイッチデータのマージをswBusでコントロール。 　　　　　　　　　--#cc/pgm　のスイッチ機能切り替え時に使用。 --------------------------------------------------------------- -- swlogics --------スイッチ回路（単体）-------------------- --------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity swParts is Port ( d : in std_logic; --sw入力 setd: in std_logic; --sw preset入力 status: in std_logic; --latch / unlatch 切り替え sel : in std_logic; --#cc/pgm 切り替え eck : in std_logic;　　　　--外部トリガー入力 sck: in std_logic; --preset取り込みトリガー q : out std_logic); --出力 end swParts; architecture RTL of swParts is signal ICK : std_logic;　　　--内部接続　クロック１ signal ICK2 : std_logic; --内部接続　クロック２ signal PR : std_logic; --内部接続　プリセット signal CLR : std_logic; --内部接続　リセット signal bufP : std_logic; --内部接続　出力用バッファ１ signal bufQ : std_logic; --内部接続　出力用バッファ２ signal bufR : std_logic; --内部接続　出力用バッファ３ begin -- ICK is internal clock ------ 外部クロックとsw入力のマージ ICK <= '1' when sel = '1' and (eck = '1' or d = '1') else '0'; --　　　　---- pgm change スイッチ制御用FF ---- -- the section for the D-FF for input data status -- process(sel,ICK) begin if sel = '0' then bufP <= '0'; elsif ((sel = '1') and (ICK'event and ICK = '1'))then bufP <= d; end if; end process; -- ---- preset data スイッチ制御用FF ---- -- The section of D-FF for preset data input -- process(sck,d,sel,setd) begin if (sel = '0') and (d = '1') and (sck = '0') then PR <= '0'; CLR <= '0'; elsif (sel = '0' and (sck'event and sck = '1')) then PR <= setd; CLR <= not setd; end if; end process; -- ---- preset data 出力用FF ---- -- The section of D-FF for preset data input -- process(sck,CLR,PR) begin if (sel = '0') and (sck = '1') then if (PR = '1' and CLR = '0') then bufR <= '1'; elsif (PR = '0' and CLR = '1') then bufR <= '0'; end if; end if; end process; -- ---- オルタネイト・スイッチ出力用FF ---- --The section of RS-FF -- ICK2 <= '1' when sel = '0' and (sck = '1' or d = '1') else '0'; process(ICK2,PR,CLR,bufQ) begin if (ICK2'event and (ICK2 = '1')) then bufQ <= ((not CLR) nor (not bufQ)) or ((not PR) and (not bufQ)); end if; end process; q <= bufP when (sel = '1') else 　　　　　　　　　　　　 ---- 出力セレクタ bufQ when (PR = '0' and CLR = '0') and (status = '1') else bufR when (PR = '1' or CLR = '1') and (status = '1') else d; end RTL; -- -- 16chFootSwStstem　　---- 16chスイッチマトリックス ---- -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity swSystem0215 is Port ( swIn : in std_logic_vector(15 downto 0); swPst : in std_logic_vector(15 downto 0); swSts : in std_logic_vector(15 downto 0); swSel : in std_logic_vector(3 downto 0); set : in std_logic; swOut : out std_logic_vector(15 downto 0); swOn : out std_logic); end swSystem0215; architecture RTL of swSystem0215 is component swParts is Port ( d : in std_logic; setd: in std_logic; status: in std_logic; sel : in std_logic; eck : in std_logic; sck: in std_logic; q : out std_logic); end component; component mux4 is Port ( d16: in std_logic_vector (15 downto 0) ; swBus: in std_logic_vector (3 downto 0); out0: out std_logic; out1: out std_logic; out2: out std_logic; out3: out std_logic); end component; signal ckIn : std_logic_vector (3 downto 0); begin ---- sw parts * 16 ---- mod15 : swParts port map( d => swIn(15), setd => swPst(15), status => swSts(15), sel => swSel(3), eck => ckIn(3), sck => set, q => swOut(15) ); mod14 : swParts port map( d => swIn(14), setd => swPst(14), status => swSts(14), sel => swSel(3), eck => ckIn(3), sck => set, q => swOut(14) ); mod13 : swParts port map( d => swIn(13), setd => swPst(13), status => swSts(13), sel => swSel(3), eck => ckIn(3), sck => set, q => swOut(13) ); mod12 : swParts port map( d => swIn(12), setd => swPst(12), status => swSts(12), sel => swSel(3), eck => ckIn(3), sck => set, q => swOut(12) ); mod11 : swParts port map( d => swIn(11), setd => swPst(11), status => swSts(11), sel => swSel(2), eck => ckIn(2), sck => set, q => swOut(11) ); mod10 : swParts port map( d => swIn(10), setd => swPst(10), status => swSts(10), sel => swSel(2), eck => ckIn(2), sck => set, q => swOut(10) ); mod9 : swParts port map( d => swIn(9), setd => swPst(9), status => swSts(9), sel => swSel(2), eck => ckIn(2), sck => set, q => swOut(9) ); mod8 : swParts port map( d => swIn(8), setd => swPst(8), status => swSts(8), sel => swSel(2), eck => ckIn(2), sck => set, q => swOut(8) ); mod7 : swParts port map( d => swIn(7), setd => swPst(7), status => swSts(7), sel => swSel(1), eck => ckIn(1), sck => set, q => swOut(7) ); mod6 : swParts port map( d => swIn(6), setd => swPst(6), status => swSts(6), sel => swSel(1), eck => ckIn(1), sck => set, q => swOut(6) ); mod5 : swParts port map( d => swIn(5), setd => swPst(5), status => swSts(5), sel => swSel(1), eck => ckIn(1), sck => set, q => swOut(5) ); mod4 : swParts port map( d => swIn(4), setd => swPst(4), status => swSts(4), sel => swSel(1), eck => ckIn(1), sck => set, q => swOut(4) ); mod3 : swParts port map( d => swIn(3), setd => swPst(3), status => swSts(3), sel => swSel(0), eck => ckIn(0), sck => set, q => swOut(3) ); mod2 : swParts port map( d => swIn(2), setd => swPst(2), status => swSts(2), sel => swSel(0), eck => ckIn(0), sck => set, q => swOut(2) ); mod1 : swParts port map( d => swIn(1), setd => swPst(1), status => swSts(1), sel => swSel(0), eck => ckIn(0), sck => set, q => swOut(1) ); mod0 : swParts port map( d => swIn(0), setd => swPst(0), status => swSts(0), sel => swSel(0), eck => ckIn(0), sck => set, q => swOut(0) ); mux01 : mux4 port map( d16(15 downto 0) => swIn(15 downto 0), ---- 4ch スイッチ・マージ swBus(3 downto 0) => swSel(3 downto 0), out3 => ckIn(3), out2 => ckIn(2), out1 => ckIn(1), out0 => ckIn(0) ); swOn <= swIn(15) or swIn(14) or swIn(13) or swIn(12) or ---- スイッチオン出力 swIn(11) or swIn(10) or swIn(9) or swIn(8) or swIn(7) or swIn(6) or swIn(5) or swIn(4) or swIn(3) or swIn(2) or swIn(1) or swIn(0); end RTL;